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| 8-bit microprocessing unit (mpu) the mc6800 is a monolithic 8-bit microprocessor forming the central control function for motorola?s m68~ family. compatible with ttl, the mc6b~, as with all m6800 system parts, requires only one + 5. o-volt power supply, and no external ttl devices for bus interface. the mc6800 is capable of addressing 64k bytes of memory with its 16-bit address lines. the 8-bit data bus is bidirectional as well as three- state, making direct memory addressing and multiprocessing applica- tions realizable. l 8-bit parallel processing l bidirectional data bus . 16-bit address bus ? wk bytes of addressing l 72 instructions ? variable length . seven addressing modes ? direct, relative, immediate, indexed, extended, implied and accumulator l variable length stack ,>: ,,*!. ?)!.ic,[ . vectored restart ? .*$ .}. ,,2:+.( ~ . maskable interrupt vector ?~? ?%1 *f. . separate non-maskable interrupt ? internal registers saved i#??::$$ ~ ..!?. stack , ~, ,)i ~. ,{). .y,:>, +, -,,,. .,,,!,. . . . . . . . . *: ,.. ?is . six internal registers ? two accumulators, index regist~#?y?:y? program counter, stack pointer and condition code re~@te~ l direct memory addressing (d ma) and multiple p~@$esso?r capability ., >s,-. .:;.!,.,, . ..+ ,? ,., l simplified clocking characteristics *v \>>>., ,**. ,1?.- ? --> ,,: +~.., ?~:?iii * . ..*? ,+< . clock rates as high as 2.0 mhz ,,:+,.. , ?.~;:),t.{t,. *:;.> , ~> l simple bus interface without ttl ,$~~~~i$~? l halt and single instruction executlo*k$~~$bility ,.*. . \ ~ ~$$~ ?;:$*y*:,f . ..., .it~ ,.,.$,.>. ?i,\ ,. *> & ?~~$ ..,. ,{, ,:&f*, >~<~? ,>$ $$:$ .~~ . . . . ~: ~+~, \*:,.: ~? ? ,*.. .+ \,\<\! ;.. ., \.j.* .+,t~ ,,,~~&y@?dering information . . w<, .-1. $,) package type ?$: ,~~equency (mhz) temperature order number ceramic+,,:, ~f~ ? 1.0 ooc to 70c mc6800l l s~~i~ ~ ? 1.0 ?40c to 85c mc~~cl @y*+(k ::: 2.0 t i. . . . . , ooc to 70c i mc68bool ~rdio 1.0 o?c to 70c mc68ws .? !?!? s suffix 1.0 ?40c to 85c mc@wcs 1.5 o?c to 70c mc68ams 1.5 ?40c to 85c mc68amcs 2.0 o?c to 70c mc68boos plastic 1.0 o?c to 70c m c6800p p suffix 1.0 ?40c to 85c mc6800c p 1.5 o?c to 70c mc68aoop 1.5 ? 40c to 85c mc68aoocp 2.0 ooc to 70c mc68boop mcwoo i i i suffix uu. - ceramic package case 715 pin assignment vss[ 10 ~ jreset halt[ 2 39 ]tsc @l [ 3 38 ]n. c. kq [ 4 37 342 vma [ 5 36 ]dbe m[ 6 35 ]n, c. ba [ 7 34 ]rl~ vccc 8 33 ] do ac [ 9 32 ]dl al [ 10 31 ] d2 a2 [ 11 30 ] d3 a3[ 12 29 ] d4 a4[ 13 28 ] d5 a5 [ 14 27 ] d6 a6 [ 15 26 ] d7 a7 [ 16 25 ]a15 a8 [ 17 24 ]a14 a9 [ 16 23 ja13 a1o c 19 22 ]a12 al 1 q 20 21 jvss motorola inc., lw ds9471-f ?? -??? -?
maximum ratings m c6~c m c68a~c i i -40to +85 i i storage temperature range i tsta l-55to +150 i ?c i thermal resistance rating symbol value unit plastic package im cerdip package ej a 60 ?clw ceramic packaqe m power considerations the average chip-junction temperature, tj, in ?c can be obtained from: tj=ta+(pdo oja) where: ta = ambient temperature, ?c this device contains circuitry to protect the inputs against damage due to high static voltages or electrical fields; however, it is ad- vised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is (1) oja= package thermal resistance, junction-to-ambient, ?c/w ;f?s ~; ,., \\wy\ ~.::$,i~ pd=pint+pport .,$ ?f:?ki,, , ,,$3 ~..,..,. . ::i~.?. ~i.:.,. pint= icc x vcc, watts ? chip internal power .<,,..,, 1*+: ,.., .,+* pport = port power dissipation, watts ? user determin@:$,,, . ,.,. . . . ,. for most applications pport< pint and can be neglected. p$o~~ may become significant if the device is configured to drive darlington bases or sink led loads. %i*\: ,+,:, ,, **f ..,,,., ,\+,* an approximate relationship between pd and tj (if ppo~~$ywbglected) is: ,.>,,,. pd= k- (tj+2730c) ~,:* (2) ., j:> solving equations 1 and 2 for k gives: ,j,t::i,} .,(*;{:\ k= pd. (ta+2730c)+0ja* pd2 . . ?}~. $ (3) ,?,::: /:?\,.*:..*>.\\ where k is a constant pertaining to the parti~$~$~~~it. k can be determined from equation 3 by measuring pd (at equilibrium) for a known ta. using this value of k the va~~~~:qft,@d and tj can be obtained by solving equations(1) and (2) iteratively for any value of ta, \\* ?:*,. .,, ,>f:?>,{,,,>i, ,t ~ ?,?., ,\<. . .~ \ ?~$,\ .,!. {w ?-.<~:,. ~~y > v?i, .\\ ,::,2.cf i?~jt:,?. . .},. dc electrical characterl~%~c~(vcc= 5,0 vdc, +5%, vss = o, ta= tl to th unless otherwise noted) ,..:$:,?,$ ,,,..,,., > ? ~~ @aracteriatic \t$.<,%,\. .&i, t. input high voltage ?i?; , ,l,, ?$, logic ?a?+$,}.,,?~ , ;>? ~.,t.. .t, 41,42 input low voltage ~w?$&~$,$# logic .,. , ?<$ ., ~? tat;.{,,, \ .:,, ~1 ,42 *,,. ;?. input leakag@:$~&f$n~ (vin =ot&@&~~, vcc= max) logic (vin ~&!0,~~@5 v, vcc=o v to 5.25 v) hi-~@bkti@akage current @l, #2 d&d7 f~#?@&.4 to 2.4 v, vcc = max) ao-a15, rlw ~w~? high voltage ?$$l load= - 205tia, vcc= minj do-d7 ?(lload= ? 1454a, vcc= min) a&a15, r/~, vma (lload= ? 100ka, vcc= min) ba output low voltage (lload = 1.6 ma, vcc = min) internal power dissipation (measured at ta = tl) capacitance (vin=o, ta=250c, f=l.o mhz) ~1 42 dgd7 logic inputs ao-a15, rl~, vma ? svmkl voh vol pint cin cout vss?0,3 ? vss+o.8 v vss?0,3 ? vss+o.4 ? 1,0 2.5 pa , [ 1 i vss+2.4 ? ? vss+2.4 ? ? v vss+2.41 ? i ? i i ? ! ? ivss+o w ,4 v ? i 0.5 ] 1,0 w i i i i ? 25 35 ? 45 70 pf ? 10 12.5 ? 6.5 10 ? ? 12 pf (m) motorola semjconducfor products inc. .- 2 clock timing (vcc= 5,0 v, *5%, vss=o, ta=tl to th unless otherwise noted) characteristic symbol min typ max unit frequency of operation mc~ 0.1 ? 1.0 mc68ao0 f 0.1 ? 1.5 mhz mcwbw 0.1 ? 2.0 cycle time (figure 1) m cm 1.000 ? 10 m c@aw tcyc o.m ? 10 ps mc~bw o.m ? 10 clock pulse width @l, @2 ? mcmn w ? 9m (measured at vcc? 0.6 v) @l, @2 ? mc6bao0 pw~h za ? 9m ns @l, @2 ? mc68bo0 180 ? 9w ,*!. ?*{,1, total 01 and 42 up time mch 90 ? .!>.,:..,.,.: ~: ~, ? y ?~:.. 600 ? ? d *?:*?:*l w ? ? ?$$:fi+s:~ ~ m c~a~ t?t mc6bbw rise and fall time (measured between vss +0.4 and vcc? o.6) tr, tf ? ? 1 delay time or clock separation (figure 1 ) , ,,,, ,,fj:$? ,i~ ,?;? ,..~? (measured at vov=vss+o.6 v@tr=tf=l~ ns) td o %$*t& ns , >+1,: ,, (measured at vov= vss + 1.0 v@tr=tf s35 ns} o ?$; y< ?$, ~ ?.$:~, ?\:i.. $ \*.?, td+ + ?d+ b,??? vl~c* . . ,, ,. ,, < ,, . ..>.,,,. .~t~ 4:. *t, ,+1 mc~ - . $~~+?<. ~a..~+,k~ mc8bao0 mc6bbo0 character@i&$if, ~~? symbol unit ~\+,\ -i min typ max min typ max min typ max *,. : address delav ,~.;.,+ -. ~?-- :$, ?:.$ . . . . . ~ ,t~,,,:y ..,,. c=90pf , ta d ? ? ,,,, 270 ? ? 1 bo ? ? 150 ns c=30 pf **3::,:> ? ? 2w ? ? 165 ? ? 135 ,,.., . . > peripheral read access ~fi&~f: tacc = tut ? (tad +~~~$~. tacc 605 ? ? m ? ? 2w ? ? ns data setup tim$,:( ~~~?: tdsr lm ? ? 60 ? ? 40 ? ? ns input data h@me ? th 10 ? ? 10 ? ? 10 ? ? ns output d~@ ?~l,#time th 10 25 ? 10 25 ? 10 25 ? ns addressf&,&,jime (address, r/~, vma) ta h 30 50 ? 30 a ? m 50 ? ns ena~~i~@time for dbe input teh 450 ? ? 280 ? ? 220 ? ? ns data ~lav time (write) tddw ? ? 225 ? ? 2w ? ? 160 ns processor controls processor control setup time tpcs 2m ? ? 140 ? ? 110 ? ? processor control rise and fall time tpcr, tpcf ? ? im ? ? 100 ? ? 100 8us available delav tba ? ? 29 ? ? 165 ? ? 135 ns hi-z enable ttse o ? 40 0 ? 40 0 ? m hi-z delav ttsd ? ? 270 ? ? 270 ? ? 220 data bus enable down time during @l up time tdbe iw ? ? 120 ? ? 75 ? ? data bus enable rise and fall times tdber, tdbef ? ? 25 ? ? 25 ? ? 25 ? m m070rola semiconductor products inc. 3 1 figure 2 ? read data from memory or peripherals / start of cycle + @l ?vihc ~ 0.4 v 7 0.4 v data not valid ~ start of cvcle ?):., [ data 2.4 v from mpu 0.4 v i k\\\\\\y data not valid ktddw+ notes: 1. voltage levels shown are vlso.4, vh> 2.4 v, unless otherwise specified 2. measurement points shown are 0.8 v and 2.0 v, unless otherwise noted @ motorola semiconductor produck inc. 4 ? figure 4 ? typical data bus output delay versus capacitive loading (tddw) 600 i oh =-205a max @ 2.4 v ?lo l=l.6mamax@0.4v 500 - vcc = 5.0 v 1a= 25c ~ 400 = u z f 300 > / ~ / ~ : 200 / ? - ~ / 100 / cl includes stray capacitance 0? 0 100 200 300 400 500 600 cl, loao capacitance (pf) figure 5 ? typical read/write, vma, and address output delay versus capacitive loading (tad) 600 lo h=-145*max@2.4v ?lo l=l.6mamax@0.4v 500 -vcc=5.ov ta = 25c -$ ,:, z 400 u z ~ 300 ~ u 0 200 100 cl includes stray capacitance o 0 100 2og~+~~ ,i$oo 400 500 600 @ motorola semiconductor products inc. 5 i figure 7 ? =panded block diagram a15 a14 a13 a12 all a1o a9 a8 a7 a6 a5 a4 a3 a2 al ao clock, @l clock, @2 reset non-maskable interrupt halt interrupt request three-state control data bus enable bus available valid memory address read/wtite, rl~ 37 40 6 a 2 3 instruction 4 decode and 39 control 36+ 34+ 1 instruction register ?*? !* ..l.t\,, @ motorola semiconductor products inc. 6 .? .? .? mpu signal description proper operation of the mpu requires that certain control and timing signals be provided to accomplish specific func- tions and that other signal lines be monitored to determine the state of the processor. clocks phase one and phase two (o1, 42) ? two pins are used for a two-phase non-overlapping clock that runs at the vcc voltage level. figure 1 shows the microprocessor clocks. the high level is specified at vihc and the low level is specified at vilc. the allowable clock frequency is specified by f (frequency). the minimum @l and @2 high level pulse widths are specified by pw~h (pulse width high time). to guarantee the required access time for the peripherals, the clock up time, tut, is specified. clock separation, td, is measured at a maximum voltage of vov (overlap voltage), this allows for a multitude of clock variations at the system frequency rate. address bus (aoa15) ? sixteen pins are used for the ad- dress bus. the outputs are three-state bus drivers capable of driving one standard ttl load and 90 pf. when the output is turned off, it is essentially an open circuit. this permits the mpu to be used in dma applications. putting tsc in its high state forces the address bus to go into the three-state mode. data bus (do-d7) ? eight pins are used for the data bus. it is bidirectional, transferring data to and from the memory and peripheral devices. it also has three-state output buffer$ capable of driving one standard ttl load and 130 pf. d,a~$, bus is placed in the three-state mode when dbe is io#t\,t w~$. ,{?.y...:>.:> ,,:!:.?.. .+,. ? +:+? ? ?$ ,. ? data bus enable (dbe) ? this level sensitive i~[~t~$sthe three-state control signal for the m pu data ~$~l:~yd will enable the bus drivers when in the high st~:&$$@j9 input is ttl compatible; however in normal op~,atib~~$twould be driven by the phase two clock. durin&@n~~,k~ read cycle, the data bus drivers will be disabled,?~~t~nal ly. when it is desired that another device contr$ptr~&ata bus, such as in direct memory access (dma)j+~k~@~ions, dbe should be held low. ~t~ .>.:,:,.,, , ,x . if additional data setup+p[+ho~d~?me is required on an mpu write, the db e down ,~,~~ @n be decreased, as shown in figure 3 (dbe#@2\r:~~e~inimum down time for dbe is tdb e as shown, ~~~.s}~ting d b e with respect to e, data setup or hold t~,$@# be increased. \\\$. ;>l:.,.?j ~, bus ay~i$~l~.(ba) ? the bus available signal will nor- mally ~%~ ~}$?low state; when activated, it will go to the ..,*.?:* y high.?ata~:+indicating that the microprocessor has stopped * ?? ??*?l+ and @,@tfhe address bus is available. this will occur if the halt~ne is in the low state or the processor is in the wait state as a result of the execution of a wait instruction. at such time, all three-state output drivers will go to their off state and other outputs to their normally inactive level. the processor is removed from the wait state by the occurrence of a maskable (mask bit i = o) or nonmaskable interrupt, this output is capable of driving one standard ttl load and 30 pf. if tsc is in the high state, bus available will be low, read/write (r/~) ? this ttl compatible output signals the peripherals and memory devices wether the mpu is in a @ motorola read (high) or wrile (low) state, the normal standby state of this signal is read (high). three-state control going high will turn read/write to the off (high impedance) state. also, when the processor is halted, it will be in the off state. this output is capable of drivina one standard ttl ioa&?iqnd 90 pf. ~+,r+i~ .:} reset ? the reset input is used to rese~&}n~&~rt the m pu from a power down condition resulti~~,jf~% a power failure or initial start-up of the processor,+:~@l%~i&el sensitive input can also be used to reinitialize t,$~~~~~ne at any time after start-up. .)? k%} ?* :t:;l, \ \ if a high level is detected in th~ inpw; this will signal the mpu to begin the reset seqe~$~. during the reset se- quence, the contents of th,~?%f$wb locations (fffe, ffff) in memory will be loade@{~~&,jtie program counter to point to the beginning of..,$~b.:wet routine. during the reset ~.\j ~t.~,,~y.. routine, the interrupt ~s~ bit is set and must be cleared under program c~~ol, before the m pu can be interrupted by irq. while ?k%jk??low (assuming a minimum of 8 clock cycles have ~jcc~$r8d) the mpu output signals will be in the followinqj$&mvma= low, ba= low, data bus= high im- peda~~e,>~~~= high (read state), and the address bus will con$&8 the ?reset address fffe. figure 8 illustrates a power ?}4 &?~q@~nce using the reset control line. after the power ~i. ~,p@ reaches 4.75 v, a minimum of eight clock cycles are ?$:jlj$~qtiired for the processor to stabilize in preparation for ?~trestarting. during these eight cycles, vma will be in an in- .lp~ determinate state so any devices that are enabled by vma which could accept a false write during this time (such as battery-backed ram) must be disabled until vma is forced low after eight cycles. reset can go high asynchronously with the system clock any time after the eighth cycle. reset timing is shown in figure 8. the maximum rise and fall transition times are specified by tpcr and tpcf. if reset is high at tpcs (processor control setup time), as shown in figure 8, in any given cycle then the restart sequence will begin on the next cycle as shown. the reset control line may also be used to reinitialize the mpu system at any time during its operation. this is accomplished by pulsing reset low for the duration of a minimum of three complete 42 cycles. the reset pulse can be completely asynchronous with the mpu system clock and will be recognized during 42 if setup time tpcs is met. interrupt request (~q) ? this level sensitive input re- quests that an interrupt sequence be generated within the machine. the processor will wait until it completes the cur- rent instruction that is being executed before it recognizes the request. at that time, if the interrupt mask bit in the con- dition code register is not set, the machine will begin an in- terrupt sequence. the index register, program counter, ac- cumulators, and condition code register are stored away on the stack. next, the mpu will respond to the interrupt re- quest by setting the interrupt mask bit high so that no further interrupts may occur. at the end of the cycle, a 16-bit ad- dress will be loaded that points to a vectoring address which is located in memory locations fff8 and fff9. an address loaded at these locations causes the mpu to branch to an in- terrupt routine in memory. interrupt timing is shown in figure 9. semiconductor products inc. 7 the halt line must be in the high state for interrupts to be serviced. interrupts will be latched internally while halt is low. the ~ has a high-impedance puilup device internal to the chip; however, a 3 kq external resistor to vcc should be used for wire-or and optimum control of interrupts. non-maskable interrupt (nmi) and wait for interrupt (wai) ? the mcwco is capable of handling two types of in- terrupts: maskable (~) as described earlier, and non- maskable (~) which is an edge sensitive input. irq is maskable by the interrupt mask in the condition code register while ~ is not maskable. the handling of these interrupts by the m pu is the same except that each has its own vector address. the behavior of the mpu when interrupted is shown in figure 9 which details the mpu response to an in- terrudt while the mpu is executina the control ~roaram. the interrupt shown could be either ~q or ~ and ca~ be asyn- chronous with respect to +2. the interrupt is shown going low at time tpcs in cycle #1 which precedes the first cycle of an instruction (op code fetch). this instruction is not ex- ecuted but instead the program counter (pc), index register (ix), accumulators (accx), and the condition code register (ccr) are pushed onto the stack, the interrupt mask bit is set to prevent further interrupts. the address of the interrupt service routine is then fetched fram fffc. fffd for an nmi interrudt and from fff8, fff9 for an ~?interrupt. upon complet~on of the interrupt ser- vice routine, the execution of rti will pull the pc, ix, accx, and ccr off the stack; the interrupt mask bit is restored to its condition prior to interrupts (see figure 10). figure 11 is a similar interrupt sequence, except in this case, a wait instruction has been executed in prepara$$~ for the interrupt. this technique speeds up the m&u??~ response to the interrupt because the stacking of tbe~~~$.w, accx, and the ccr is already done. while t~~$fm@ is waiting for the interrupt, bus available wilp&@+{q?~h in- dicating the following states of the control lj~~y~ma is low, and the address bus, r/~and data b~~ ~~, ~{ in the high impedance state. after the interrupt w-$* is serviced as previously described. ,.\, .< },it?~ ,,,:: a 3-10 kq external resistor to v&*?&~&tild be used for wire- or and optimum control of igi~r~w~t~. ,*+ $ . .,,. ?$,? . . memory map.@r imrrupt vectors ~ :.$ ?*, ,,$? vetior ,.., ;. ?~? ms ,,f*y description fffe :,* e=3 reset fffq?j? %ffd non-maskable interrupt e&.~\x}i, ,$ fffb software interrupt ?$,~aip? ~ ? interrupt request three-state control (tsc) ? when the level sensitive three-state control (tsc) line is a logic ?l?, the address bus and the rim line are placed in a high-impedance state. vma and ba are forced low when tsc= ?1? to prevent false reads or writes on any device enabled by vma. it is necessary to delay program execution while tsc is held high. this is done by insuring that no transitions of 41 (or 42) occur during this period. (logic levels of the clacks are irrele- vant so long as they do not change). since the mpu is a dynamic device, the 01 clock can be stopped for a maximum @ motorola time pw@h without destroying data within the m pu. tsc then can be used in a short direct memory access (dma) application. figure 12 shows the effect of tsc on the mpu. tsc must have its transitions at ttse (three-state enable) while holding +1 high and +2 low as shown, the address bus and rl~ line will reach the high-impedance state at ttsd (three-state delay), with vma being forced low. in this exampl$~%the data bus is also in the high-impedance state while,,~;~@&- ing held low since dbe= 42. at this point in ti@e~,$,?)~ma transfer could occur on cycles #3 and #4. -+$~sc is returned low, the mpu address and r/~lfl&/&mrn to the bus. because it is too late in cycle #5 to,,~cp~,~emory, this cycle is dead and used for synchroni$~~w.i$~rogram execu- tion resumes in cycle #6. ..>;. .*? .!~:l .?~\k:\, .:~:.3, ~.:~? ?1~$ ~ valid memory address (vm&,~~$ this output indicates to peripheral devices that the~@&.@~a~?d address on the address bus. in normal operation~ 1 to debug programs it is advantageous to step through iinesare back on the bus. asingle byte, 2 cycle instruction programs instruction byinstruction .to do this, halt must such as lsrisused forth isexample also. during the first cy- be brought high for one mpu cycle and then returned low as cle, the instruction y is fetched from address m+l. ba shown at point b of figure 13. again, the transitions of returns high at tba on the last cycle of the instruction in- halt must occur tpcs before the trailing edge of $1. ba dicating the mpu is off the bus. if instruction y had been will go low at tba after the leading edge of the next @l, in- three cycles, the width of the ba low time would have been dicating that the address bus, data bus, vma and rl~ increased by one cycle. figure 10 ? mpu flowchart f y 1 +ba 3 y l i 1 1. 2 3 0 a reset is recognized at any position in the flowchart. instructions which affect the l-bit act upon a on~bh buffer register, ?ltmp.? this has the effect of delaying any clearing of the l-bit one clock time. setting the l-bit, however, is not delayed. see tables 6-11 for details of instruction execution. m motorola semiconductor products inc. 10 address bus r/r vma interrupt irq or m data bus ba figure 11 ? wait instruction timing i cycle i i i i i i i i i #1 * * #4 * & #7 #8 * #1 o n n+l n+2 new pc address x x x x x x x instruction \ 1[ first inst of interrupt routine x x x x x x x x x x x x wait pc 0-7 pc 8-15 i 0-7 i b-15 acca accb new pc 8-15 new pc o-7 i nst [[ address address a note: midrange waveform indicates high imdedance state. -tba figure 12..+$tike-state control timing 1 @l @z m ba vma r/% address bus data bus figure 13 ? halt and single instruction =ecution for system debug m instruction instruction instruction fetch execute \ / xy x {1 )) x xy fetch exwute addr m x ., , :.~~>), the m pu has three 16-bit registers and thra-$,8~*@ registers available for use by the programmer ( fj$?@?~d@. *.y -i:,., ~~> ,$ program counter ? the program count~$&~?:?&t&o byte (16 bits) register that points to the curre~~,?w~$m address. , +$, ?~,i stack pointer ? the stack pon~*i~%,;&o byte register that contains the address of the ne&,,a$ilable location in an external push-down/pop-up st$~~$~fs stack is normally a random access read/write,,,%b*~.#??that may have any loca- tion (address) that is conv@iej~t. in those applications that require storage of inf@~atidb? in the stack when power is lost, the stack muskl~~~~volatile. , .,,, $:.,,, ~?, .. index rwis~~~~~$%e index register is a two byte register that is used x~i$~$?data or a sixteen bit memory address for the lnde&& &&e of memory addressing. ;8 * ,.:,. :$.,,, {.. . . . . . ..\..:+l.\:!!i, aq~$#~ators ? the mpu contains two 8-bit ac- cwuktprs that are used to hold operands and results from a~~{~~metic logic unit (alu). ... condition code register ? the condition code register in- dicates the results of an arithmetic logic unit operation: negative (n), zero (z), overflow (v), carry from bit 7 (c), and half carry from bit 3 (h). these bits of the condition code register are used as testable conditions for the condi- tional branch instructions. bit 4 is the interrupt mask bit (l). the unused bits of the condition code register (b6 and b7) are ones. @ motorola figure 14 ? programming model of the microprocessing unit pc 15 0 sp 7 m llt o w inzvc carrv (from bit 7) overflow accumulator a accumulator b index register program counter stack pointer condition code registar ii - zero r ;:::t half carrv (from bit 3) semiconductor products inc. 12 -. ?. mpu instruction set the mc~ instructions are described in detail in the when an instruction translates into two or three bytes of mww programming manual. this section will provide a code, the second byte, or the second and third bytes con- brief introduction and discuss their use in developing tain(s) an operand, an address, or information from which an mc~ control programs. the mc66w has a set of 72 dif- address is obtained during execution. ferent executable source instructions. included are binary microprocessor instructions are often divided into three and decimal arithmetic, logical, shift, rotate, load, store, general classifications: (1) memory reference, so called conditional or unconditional branch, interrupt and stack because they operate on specific memory locations; (2) manipulation instructions. operating instructions that function without needing a each of the 72 executable instructions of the source memory reference; (3) 1/0 instructions for transferring data language assembles into 1 to 3 bytes of machine code. the between the microprocessor and peripheral devices. $+cl+ number of bytes depends on the particular instruction and in many instances, the m cm performs the sarn?$*a- on the addressing mode. (the addressing modes which are tion on both its internal accumulators and ~#r@rnal available for use with the various executive instructions are memory locations. in addition, the mc%:,~@terface discussed later, ) adapters (pia and acia) allow the mpu t~$~~~k~peripheral the coding of the first (or only) byte corresponding to an devices exactly like other memory loca@~$.3@#nce, no 1/0 executable instruction is sufficient to identify the instruction instructions as such are required. beca&wq@these features, and the addressing mode. the hexadecimal equivalents of ?$ ,? ~ other classifications are more sui~@fl~&~~b~ introducing the the binary codes, which result from the translation of the 72 mc66ws instruction set: (1) ,$cc?%hlator and memory instructions in all valid modes of addressing, are shown in operations; (2) program cont~~t~perations; (3) condition table 1. there are 197 valid machine codes, 59 of the 256 ~ i~~~ code register operations, ,,,~~~~, % possible codes being unassigned. ~~-~ ,,, , .,,\., , ,\ 1 ----- - . . . . . . . . . ---- . . . . . . . . . . . . . ---- .-,-. ,- lablt z ? aluumulaiur and mtmumy urernat iun> operations mnemonic add add acmltrs add wlfh carry and blt tesl clear compare compare acmltrs complement, 1?s complement, 2?s (negate) dec!mal adi.st, a decrement exci?si?e or increment load acmltr or, inclusive push oata pull oata rotate left rotate r,ght shift left, ar!thmet!c sh[ft right, arfthmet!c sh!f! right, logic store acmltr. subtract subtracf acmltrs. adda adob aba aoca aocb anda anob bita bite clr clra clrb cmpa cmpb cba com coma comb neg nega negb oaa oec oeca oecb eora eorb inc inca incb loaa ldab o raa orab psha ?shb pu la pu lb rol rola rolb ror rora rorb asl asla aslb asr asra asrb lsr lsra lsrb arithmetic minus; boolean ano: msp contents of memow location pointed to be stack pointer: boolean inclusive or; & boolean exclusive or; m complement of m; + transfer into; o bit = zero; 00 byte = zero; aooressing mooes extno inoex 1p-= con ottion code symbol5 h hal f.carrv from bit 3; i interrupt mask n negative (tign bit) z zero (byte) v ovetilow, 2?s complement c carv from bit 7 r rewt always s set alwav$ implieo 1p-= b21 f21 f21 121 1321 i321 lo2f io21 1921 ia21 ,a21 1c21 ic21 !9 2 j9 2 !6 2 j6 2 $8 2 58 2 a7 2 57 2 44 2 54 2 10 2 16 2 17 2 $0 2 50 2 1 1 1 i 1 1 1 1 1 1 1 1 1 1 1 i 1 1 1 ? boolean/arithmetic operatf on (all register labels refer to contents) a+ m-a b+m+b a+ msp, sp-f-sp b-, msp, sp?l+sp sp+i-sp, msp-a sp+i+sp, msp-b m a b }l-??????j c b7 - bo m a b lk-?????[d c b7 ? bo m a } o-~ - 0 b b7 bo c a?-m b-m a? m-a b? m-b a? b-a a?m? c-a b- m? c-b a-b b-a m?00 a?00 b?do con oition cooe register notes: (bit set if testis true and cleared otherwise] 1 (bit v) test: result = 1000oooo7 2 (bit c) test: result = 000000007 3 (bit c) test: oecimal value of most significant bco character greater than nine? ( not cleared if previously set.] 4 (bit v) test: operand= 10000000 prior to execution? 5 (bit v) test: operand= 01111111 prior to execution? t test and set if true, cleared otherwise 6 (bit v) test: set equal to result of n@c after shift has occurred l not affected note ? accumulator addresbng mode instructions are included in tho column for implieo addressing @ motorola semiconductor products inc. 14 .- .? -. program control operations program control operation can be subdivided into two categories: (1) index register/ stack pointer instructions; (2) jump and branch operations. index register/ stack pointer operations the instructions for direct operation on the mpu?s index register and stack pointer are summarized in table 3. decrement (dex, des), increment (inx, ins), load (ldx, lds), and store (stx, sts) instructions are provided for both. the compare instruction, cpx, can be used to com- pare the index register to a 16-bit value and update the con- dition code register accordingly. the tsx instruction causes the index register to be load- ed with the address of the last data byte put onto the ?stack. ? the txs instruction loads the stack pointer with a value equal to one less than the current contents of the index register. this causes the next byte to be pulled from the ?stack? to come from the location indicated by the index register. the utility of these two instructions can be clarified by describing the ?stack? concept relative to the m@w system. the ?stack? can be thought of as a sequential list of data stored in the mpu?s read/write memory. the stack pointer contains a 16-bit memory address that is used to access the list from one end on a last-in-first-out (lifo) basis in contrast to the random access mode used by the mpu?s other ad- dressing modes. the mc~ instruction set and interrupt structure allow extensive use of the stack concept for efficient handling of data movement, subroutines and interrupts. the instructi~.os can be used to establish one or more ?stacks? anywhg~~~< read/write memory. stack length is limited only <,q~$~~e amount of memory that is made available. .,is,~ ,., operation of the stack pointer with the pus@,@i~~,rtill in- structions is illustrated in figures 15 and 1~~..%~.$ush in- struction ( ps ha) causes the contents of kd$~~icated ac- cumulator (a in this example) to be stor~+in;wemory at the location indicated by the stack point@r. ~q&stack pointer is automatically decremented by ~~~~$~t~wing the storage operation and is ?pointing? to th~~:~e{$empty stack location. the pull instruction (pula ..@~:~%?b) causes the last byte stacked to be loaded intothe:w?ropriate accumulator. the stack pointer is automatically incremented by one just prior to the data transfer so that it will point to the last byte stack- ed rather than the next empty location. note that the pull instruction does not ?remove? the data from memory; in the example, 1 a is still in location (m+ 1) following execution of pula. a subsequent push instruction would overw~jt~~at location with the new ?pushed? data. ? ..$.,,,.$,. *,.,,.: i:~).:~ ~.f.,k\, execution of the branch to subroutine (b sr)a$d. #~rrfp to subroutine (jsr) instructions cause a returd%~*~ to be saved on the stack as shown in figures 18$~w~@ 20. the stack is decremented after each byte of,.#$r@?n address is pushed onto the stack. for both of$&~~n@structions, the return address is the memory locatid~ f~jo?wing the bytes of code that correspond to the b,s$.:an?~:$&sr instruction. the code required for bsr or j g~g?~ i figure 15 ? stack operation, push instruction sp~m .{ei m+l 7f previously stacked m+2 63 data m+3 fd ?c-- (a) before psha mpu m ~?q..i, % (b) aftar psha pc ~ pula next in$tr. mpu i i i acca m i m?2 m?1 m sp+m+l { mt2 previously stacked m+3 data i 1a 3c d5 \ p (b) after pula (a) before pula m motorola semiconductor products inc. 16 ? ? operations branch always branch if carry clear branch if carry set branch if = zero branch if > zero branch if >zero branch if higher branch if < zero branch if lower or same branch if < zero branch if minus branch if not equal zero branch if overflow clear branch if ovefilow set branch if plus branch to subroutine jump jump to subroutine no operation return from interrupt return from subroutine so ftwre interrupt wait for interrupt% iai puts address bus, rn, and mnemonic bra bcc b cs beo bge bgt bhi ble b ls b lt bmi bne bvc bvs bpl bsr jmp jsr nop rti rts swl wai ita businthet table 4 ? jump and branch instructions cono. cooe reg. re g g 24 25 27 2c 2e 22 2f 23 20 2b 26 28 29 2a 80 ~ hl ? y 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 ? ?n t ? # t 2 2 2 2 2 2 2 2 2 2 2 z 2 2 2 ~ ? g ? 6e ao m low i ? ? 3 9 ? ? ? # ? 3 3 ? ..? l i i i i i @ (all) load condition code register from stack. (see special op$@tic ? branch test t 10 vc is required to exit the wait state. execution of the jump instruction, jmp, and branch always, bra, affects program flow as shown in figure 17. when the mpu encounters the jump (indexed) instruction, it adds the offset to the value in the index register and %, the result as the address of the next instruction to~b~;~x~$ ecuted. in the extended addressing mode, the add[e~~~?he next instruction to be executed is fetched from ,$~$~*~~ca- tions immediately following the jm p instructl~~~}k~wbranch always (bra) instruction is similar to the j~~?~#~&nded) in- struction except that the relative addre&sin&. fiode applies and the branch is limited to the rang~wtkm$- 125 or + 127 bytes of the branch instruction i~$~}%%.~~e opcode for the ~4,i. . ?.., ,..\. ?,,$< ? bra instruction requires one les$by~ than j m p (extended) but takes one more cycle to @? the effect on program fl~~ f$r the jump to subroutine (jsr) and branch to sw#rqu{*$ (bsr) is shown in figures 18 through 20. note t~%:$@program counter is properly in- cremented to be$:~~~:n~ at the correct return address before it is stac~&i,;~~#~ration of the branch to subroutine and jump to a~w~?tine (extended) instruction is similar ex- cept for th@~~n~&> the bs r instruction requires less opcode than j $$&r{%q~#es versus 3 bytes) and also executes one cy - ~ (bit 1 ) set when interrupt occurs. if previously set, a non-mask,:~e??%?errupt ~+. ?~ .* ?+~?$.. used as the end of a subroutine to return to the main pro- ~y : gram as indicated in figure 21, the effect of executing the software interrupt, swi, and the wait for interrupt, wai, and their relationship to the hardware interrupts is shown in figure 22. sw! causes the m pu contents to be stacked and then fetches the starting address of the interrupt routine from the memory locations that respond to the addresses fffa and fffb. note that as in the case of the subroutine instructions, the program counter is incremented to point at the correct return address before being stacked. the return from interrupt instruction, rti, (figure 22) is used at the end of an interrupt routine to restore control to the main program. the swi instruction is useful for inserting break points in the control program, that is, it can be used to stop operation and put the mpu registers in memory where they can be examined. the wai instruction is used to decrease the time required to service a hardware interrupt; it stacks the mpu contents and then waits for the interrupt to occur, effectively removing the stacking time from a hardware interrupt sequence, figure 17 ? program flow for jump and branch instructions [x+k ~ [ ,,-, (n+2)*klxl l k = signed 7-bit value (a) jump (b) branch m motorola semiconductor products inc. 17 i figure 18 ? program flow for bsr a (n +2)h -. sp~m?2 m?1 m m+l n n+l n+2 ? + 1 ] tk = offset* i n+ 2 i next main l?str. i * k = signed 7-bit value (a) before execution , ~i)::~? \ ,\~.,, figure 19 ? program flow for jsr (~tendem,\ ?%, figure 20 ? program flow for jsr (lndwed) r m?1 (n+2)h m (n+2)l m+l 7e 7a ? m?l sp?m m+l b 7e 7a pc_n a jsr=ad n+l k = of fset? ?+2 next main l?str. ? g jsr = ad ?+1 k = offset ?+2 next main l?str. ?1 js r i n+ 2 i sl=sub,. addr, i l k = 8-bit u?sig?ed value pc+ x.+k 1st s.br, instr. 1 r 1 (a) before ex%utton ??s= ?contents of index register (a) before execution (b) afrer execuxion (s formed from sh and sl) 1 (b) after execution motorola semiconductor products inc. 18 sp-m?2 m?1 m m+l n n+l nt2 nt3 figure 21 ? program flow for rts h m?2 (n+3)h m?1 sh = subr. addr. n+l sl = subr. addr. n+2 i b last subr. instr. r ts pc ? j s? a last inter. i nstr. rti flow for rti m?7 m?6 m?5 m?4 m?3 m?2 m?1 sp~ m pc? ?+1 s? ccr accb acca x~ xl pch 4 pcl 7e i next main i?str. i i last s?br. instr. i (a) before execution (b) after execution @ motorola semiconductor products inc. 19 i figure ~ ? program flow for interrupts wait for hardware interrupt or interrupt nonmaskable interrupt (nmi) .- software lnterrudt main program? n:=. main program main program :1= n- 7? sp + stack mpu register contents m?7 m?6 m?5 m?4 m?3 m?2 m?1 m wi fff8 fffc fff9 fffd fffe ffff d set interrupt mask (ccr 4) interrupt memorv assignment fff8 i irq i ms fff9 irq ls fffa swl ms fffb swl ls # first instr. e bvfetching addr. formed q load interrupt vector into 2. eytes from program counter per, mere, assign. f a i nterruot proaram > ,. 1 lstlnterruutlnstr. 1 note: ms= most significant address bvte; ls = least s~nificant address byte; i 1 @ motorola semiconductor products inc. 20 figure 24 ? conditional branch instructions bmi : n=l ; beq : z=l ; bpl : n=@ ; bne : z=4 ; bvc : v=$ ; bcc : c=$ ; bvs : v=l ; bcs : c=l ; bhi : c+ z=@ ; blt : n@v=l ; bls : c+z=l ; bge : n@ v=@ ; ble : z+(n@v)=l bgt : z+(n@v)=@ ; the conditional branch instructions, figure 24, consists of seven pairs of complementary instructions. they are used to test the results of the preceding operation and either con- tinue with the next instruction in sequence (test fails) or cause a branch to another point in the program (test suc- ceeds). four of the pairs are used for simple tests of status bits n, z, v, and c: 1. branch on minus (b mi) and branch on plus (bpl) tests the sign bit, n, to determine if the previous result was negative or positive, respectively. 2. branch on equal (beq) and branch on not equal (bne) are used to test the zero status bit, z, to determine whether or not the result of the previous operation was equal to zero. these two instructions are useful following a com- pare (cmp) instruction to test for equality between an ac- cumulator and the operand. they are also used following the bit test (bit) to determine whether or not the same bit pos~~ tions are set in an accumulator and the operand. >.t;.?: ,y). . ...,.,, ~ 3. branch on overflow clear (bvc) and branc@$~ns overflow set ( bvs) tests the state of the v bit to ~&~*e if the previous operation caused an arithmetic q@r,@~ 4. branch on carry clear (bcc) and branch @~b$ry set ( bcs) tests the state of the c bit to determ~~$$~~~previous operation caused a carry to occur. bcc ~~,~~~b are useful .,*.j?,? -~>, ?:? condition for testing relative magnitude when the values being tested are regarded as unsigned binary numbers, that is, the values are in the range 00 (lowest) to ff (highest). bcc following a comparison (cmp) will cause a branch if the (unsigned) value in the accumulator is higher than or the same as the value of the operand. conversely, bcs will cause a branch if the accumulator value is lower than the operand. the fifth complementary pair, branch on higher (qi&~~~,nd branch on lower or same (bls) are, in a se~~~/~@~- plements to bcc and bcs. bhi tests for both c ~n@~~o; if used following a cmp, it will cause a branc~,?k~~pwalue in the accumulator is higher than the oper&~~%50nversely, bls will cause a branch if the unsignq~?~~a~??value in the accumulator is lower than or the saw:~$j&b operand. the remaining two pairs are u~~l ~ ?testing results of operations in which the values at% re&~yded as signed two?s complement numbers. this $%&&}{rom the unsigned binary case in the following sen:~+~~.{~nsigned, the orientation is higher or lower; in si~w?~,wo?s complement, the com- parison is between @$~~g~&~ smaller where the range of values is between ? 1~,.,and + 127. branch on l@$~$anzero (blt) and branch on greater than or eq~#k.~~~?~~g e) test the status bits for n @v= 1 and n e v{~$<,,r~pectively. b lt will always cause a branch followin$~~s 8~~ration in which two negative numbers were adde,~. in?~dition, it will cause a branch following a cmp in wh#~$jhe value in the accumulator was negative and the ,@$&~~n?& was positive. b lt will never cause a branch follow- .,:t~@,$#cmp in which the accumulator value was positive and ,,+,. we operand negative. bge, the complement to blt, will {f$:,,.j ..::} ?*n cause. a branch following operations in which two positive ,+ ::> values were added or in which the result was zero. the last pair, branch on less than or equal zero (ble) and branch on greater than zero (bgt) test the status bits for z@ (n+v) = 1 and z@ (n +v) =0, respectively. the ac- tion of ble is identical to that for blt except that a branch will also occur if the result of the previous result was zero, conversely, bgt is similar to bge except that no branch will occur following a zero result. code register ? i$,:,i ;;* ,,,1.,. . . .,.y ~ operations . . ??s$.~$$:? ,, ?$?.,, l~~k,j.f the condition ~~~~register (ccr) is a 6-bit register to precede any sei instruction with an odd opcode ? such within the mpu~~~kl$*useful in controlling program flow as nop. these precautions are not necessary for mc~ during system d;%tlon. the bits are defined in figure 25. processors indicating manufacture in november 1977 or the instr~~lia~% shown in table 5 are available to the user later. for dire~#~@@@ulation of the ccr. systems which require an interrupt window to be opened a c~,$a/ instruction sequence operated properly, with under program control should use a cli-nop-sei sequence earl~:~~$~~ processors, only if the preceding instruction rather than cli-sei. was $~d (least significant bit= 1), similarly it was advisable @ motorola semiconductor products inc. 21 l co nd. cooe reg. e = boolean operation 1 o+c 1 0+1 1 o+v 1 l+c 1 1+1 1 l-v 1 a+ccr 1 ccr+a m hi nzvc l 00m* r l r**** l .mm r. l ore** s l s. *q. l **o s. w l l l \* l l the m p&%~&$ates on 8-bit binary numbers presented to it via the..~t~~~?{~us. a given number (byte) may represent eithe&~{~~@:or an instruction to be executed, depending on w@.@/~,~s encountered in the control program. the mm ha$~~tinique instructions, however, it recognizes and takes actloh on 197 of the 256 possibilities that can occur using an 8-bit word length. this larger number of instructions results from the fact that many of the executive instructions have more than one addressing mode. these addressing modes refer to the manner in which the program causes the mpu to obtain its instructions and data. the programmer must have a method for addressing the mpu?s internal registers and all of the external memory loca- tions. selection of the desired addressing mode is made by the user as the source statements are written. translation into @ motorola appropriate opcode then depends on the method used. if manual translation is used, the addressing mode is inherent in the opcode. for example, the immediate, direct, indexed, and extended modes may all be used with the add instruc- tion. the proper mode is determined by selecting (hex- adecimal notation) 8b, 9b, ab, or bb, respectively. the source statement format includes adequate informa- tion for the selection if an assembler program is used to generate the opcode. for instance, the immediate mode is selected by the assembler whenever it encounters the ?#? symbol in the operand field. similarly, an ?x? in the operand field causes the indexed mode to be selected. only the relative mode applies to the branch instructions, therefore, the mnemonic instruction itself is enough for the assembler to determine addressing mode. semiconductor products inc. ~ 22 ?. for the instructions that use both direct and extended ?operands? but the space between them and the operator modes, the assembler selects the direct mode if the operand may be omitted. this is commonly done, resulting in ap- vaiue is in the range o-255 and extended otherwise. there parent four character mnemonics for those instructions. are a number of instructions for which the extended mode is the addition instruction, add, provides an example of valid but the direct is not. for these instructions, the dual addressing in the operand field: assembler automatically selects the extended mode even if the operand is in the o-255 range. the addressing modes are operator operand comment summarized in figure 26. adda mem12 add contents of mem12 to j&~$:k or . t;.., inherent (includes ?accumulator addressing? mode) ~ ~,~~1~$~ ,,?~ ..:$ addb mem12 add contents of mem12 %q #&c~ the successive fields in a statement are normally i.;~:, ,,, ~ , ;i, \.jtj$+t?$ separated by one or more spaces. an exception to this rule the example used earlier for the test instru~&~~?st, also occurs for instructions that use dual addressing in the applies to the accumulators and uses th,$~~~~ohulator ad- operand field and for instructions that must distinguish re- dressing mode? to designate which o$,,x?v-accumulators tween the two accumulators. in these cases, a and b are is being tested: \,*\ ~$.;: .~#<:,\, ~:; .jt .\~; , . . direct: n do instruction example: subb z addr. rane = o?255 a n+l z = oprnd address n+2 next instr. (k = one-bvte oprnd) l z& or .:,,. (k = two-bvte oprnd) (k = one-bvte oprnd) (k = two-bvte oprnd) j ntl zh = oprnd addr-s n+2 zl = oprnd address n+3 next instr. . l z& or z [ kh = operand i *?r, n+2 next inst. or n+2 i kl = operand i n+3 i next instr. i relative: n i instruction i example: bne k (k = signed 7-bit value) addr. range: ?125t0 +129 relative to n. l l (?+2)?k- ~ if br?ch tst false, ~ if brnch tst true. indexad: n instruction i example: adda z, x ?+1- addr. range: n+2 i next instr. o?255 relative to 1 index register, x o l (z = a-bit unsignad value) x+z& @ motorola semiconductor products inc. q9 1 * :?@ o operator comment mode, the ?address? of the operand is effectively the tstb test contents of accb memory location immediately following the instruction itself. or table 7 shows the cycle-by-cycle operation for the im- tsta test contents of acca mediate addressing mode. a number of the instructions either alone or together with direct and extended addressing modes ? in the direct an accumulator operand contain all of the address informa- tion that is required, that is, ?inherent? in the instruction itself. for instance, the instruction aba causes the mpu to add the contents of accumulators a and b together and place the result in accumulator a. the instruction incb, another example of ?accumulator addressing,? causes the contents of accumulator b to be increased by one. similarly, inx, in- crement the index register, causes the contents of the index register to be increased by one. program flow for instructions of this type is illustrated in figures 27 and 28. in these figures, the general case is shown on the left and a specific example is shown on the right. numerical examples are in decimal notation. instructions of this type require only one byte of opcode. cycle-by-cycle operation of the inherent mode is shown in table 6. immediate addressing mode ? in the immediate address- ing mode, the operand is the value that is to be operated on. for instance, the instruction oper*or operand comment ldaa #25 load 25 into acca causes the m pu to ?immediately load accumulator a with the value 25?; no further address reference is required. the immediate mode is selected by preceding the operand value with the ?#? symbol. program flow for this addressing m,~de is illustrated in figure 29. y..\ .*., .j.$,i~>>, the operand format allows either properly define$:$ym bols or numerical values. except for the instru~ti~~?wx, ldx, and lds, the operand may be any valu~,i~:~e,;~nge o to 255. since compare index register (c&,~q$.~~&?d index register (ldx), and load stack pointer (~$~;.$e~uire 16-bit values, the immediate mode for these~%re~+ ~tistructions re- quire two-byte operands. in th~:t~,yate addressing 4 program memory pc instr general flow pc = 5000 mpu @ index a ram z prog ram memory inx t i example and extended modes of addressing, the operand field of the source statement is the address of the value tha$+i$j~o be operated on. the direct and extended modes d~ff~$:fi$y in the range of memory locations to which they ~$~~trect the m pu. direct addressing generates a sin~l~.~~%~ operand and, hence, can address only memory l@~&&~?& o through 255; a two byte operand is generated~{&~qex&&~ded address- ing, enabling the mpu to reach theik~~~j&?hg memory loca- tions, 256 through 65535. an ex~&pl$ o* direct addressing and its effect on program flo,~~~ ~&lrated in figure 30. the m pu, after encoun\ew@<~e opcode for the instruc- tion ldaa (direct) at,~~ary location 5004 (program counter= 5004), look~~~~$~:~next location, 5005, for the ad- dress of the operan~$~~~{~~ sets the program counter equal to the value foun@ t~~{~100 in the example) and fetches the operand, in t~~~$$e a value to be loaded into accumulator a, from th,~+~p~$$n. for instructions requiring a two-byte operande$~hk~ ldx (load the index register), the operand bytes $+~4&be retrieved from locations 100 and 101. table 8 sh%~ws t~~ cycle-by-cyc4e operation for the direct mode of a*~ssi ng, ,~~?+i$xt~nded addressing, figure 31, is similar except that a :t:~:+~@-byte address is obtained from locations 5007 and 5008 ~~,,.$$tafter the ldab (extended) opcode shows up in location ?e$s 5006. extended addressing can be thought of as the ?stan- ~y>t,$ dard? addressing mode, that is, it is a method of reaching any place in memory. direct addressing, since only one ad- dress byte is required, provides a faster method of process- ing data and generates fewer bytes of control code. in most applications, the direct addressing range, memory locations o-255, are reserved for ram. they are used for data buffer- ing and temporary storage of system variables, the area in which faster addressing is of most value. cycle-by-cycle operation is shown in table 9 for extended addressing. figure z ? accumulator addressing mpu f ram program memory b pc w instr general flow m pu m accb m ram a program memory pc = 5001 inc b example @ mororola semiconductor producfs inc. 24 ? ? -. relative address mode ? in both the direct and extended the unconditional jump (jmp), jump to subroutine (jsr), nodes, the address obtained by the mpu is an absolute and return from subroutine (rts) are used. ~umerical address. the relative addressing mode, im- in figure 32, when the mpu encounters the opcode for )iemented for the mpu?s branch instructions, specifies a beq (branch if result of last instruction was zero), it tests the nemory location relative to the program counter?s current zero bit in the condition code register. if that bit is ?o,? in- dcation. branch instructions generate two bytes of machine dicating a non-zero result, the mpu continues execution :ode, one for the instruction opcode and one for the with the next instruction (in location wio in figure 32). if the ?relative? address (see figure 32). since it is desirable to be previous result was zero, the branch condition is satisfied ible to branch in either direction, the 8-bit address byte is in- and the mpu adds the offset, 15 in this case, to pc+ 2 and erpreted as a signed 7-bit value; the 8th bit of the operand is branches to location w25 for the next instruction. rested as a sign bit, ?o?= plus and ?1?= minus. the re- the branch instructions allow the programmer to efficient- naining seven bits represent the numerical value. this iy direct the mpu to one point or another in the contro$.:~ro- esults in a relative addressing range of * 127 with respect to gram depending on the outcome of test results. ~w~%e he location of the branch instruction itself, however, the control program is normally in read-only memory #ti~$@not )ranch range is computed with respect to the next instruc- be changed, the relative address used in execu@~~@t&ranch ion that would be executed if the branch conditions are not instructions is a constant numerical valuq~?~~~@-by-cycle iatisfied. since two bytes are generated, the next instruction operation is shown in table 10 for relatig& a~q@ssing. s located at pc + 2. if d is defined as the address of the .}:\a ,# ? ~, \ .!-, s. ,,i , )ranch destination, the range is then: indexed addressing mode ? ~~~~d~xed addressing, -!l!,., ,, (pc+2)? 127 sd s(pc+2)+127 the numerical address is variable qnd d~ends on the current )r contents of the index register@~~$ource statement such as .+:y> pc?125 table 6 ? inherent mooe cycle-by-cycle operation (continued) i address mode cvcle vma r lx and instructions cycles # line address bus line data bus wa i 1 1 op code address 1 op code 2 1 op code address + 1 1 op code of next instruction 3 1 stack pointer o return address (low order byte) 4 1 stack pointer ? 1 0 return address (high order byte) ?q,,x, 9 5 t:f,s :.,. ;:~;$$ * 1 stack pointer ? 2 0 index register (low order by&g].;;.;? ~ ?..* .,> ! ~{$ 6 1 stack pointer ? 3 0 index register (high ord:[o &#}$ 7 1 stack pointer ? 4 0 contents of accumula~~. ~~p~ ?p .?., ,, .\{..> ~,* r<,+ 8 1 stack pointer ? 5 0 contents of accurn,~taym $: 9 1 \%*~, \. stack pointer ? 6 (note 3) 1 contents of condf@5~,segister rti 1 1 op code address 1 op code ..*, i., .:.$., )yp ,t,\,+ .a>~+m ., 2 1 op code address+ 1 1 irrelevant ~ata ~@te 2) 3 0 stack pointer 1 lrreleva$$k~~a (note 1 ) . ..*;,*,\, ,~< ~.+,>+ ?..,.> 4 1 stack pointer + 1 1 corw~&~ti cond. code register from s*.@? ,,s. 10 .\i?... ..3:, ~ *., 5 1 stack pointer + 2 %ts of accumulator b from stack 1,4 :#&q$ 6 1 stack pointer + 3 .3**: ?%ntents of accumulator a from stack 7 1 stack pointer + 4 ?f$ac ~y~e~ register from stack (high order 8 1 stack pointer + 5 index register from stack ( low order byte) 9 1 stack pointer + 6 , >;: next instruction address from stack ,,, ,.?, :*. ?\.*: , (high order byte) 10 1 stack pointer + 7 ,,,.y;,:,~, ,,. ~;? ~...k. 1 next instruction address from stack ,$ ~!?>i, ,;i) (low order byte) .+ \ \ ..,, . . . . . sw i 1 1 op code addresq&+,t~s 1 .op code ,, 2 1 op code address ~{~ 1 irrelevant data (note 1 ) 3 1 stack poi$ter ~; o return address (low order bvte) ,><~. 4 1 stack ,~in~~ ? 1 0 return address (high order byte) 5 1 sta*~hter ? 2 {!,<, o index register (low order byte) - . . . 12 6 1 :@~ok%~inter ? 3 0 index register (high order byte) ~ ?..s,:...,nty? .* j 1 >j$ ?:;t*,# pointer ? 4 0 contents of accumulator a ,.::,, /.. ,:~< , .,:>, 8 ,,{?!~$$ ;$tack pointer ? 5 0 contents of accumulator b %~i> ,:,,i:\$\ i? , $1 ? stack pointer ? 6 0 contents of cond. code register $:to ; 6 :r$o stack pointer ? 7 1 irrelevant data (note 1 ) .>?+ ):$w,$ 1 vector address fffa (hex) 1 address of subroutine (high order ,~ $.} :;,* :, byte) ??? ?? ?;? 12 1 ,$, . .j$, * .,. .> :.$ vector address fffb (hex) 1 address of subroutine (low order . ...% , :.+;l+ ,.:y byte) t$.~ ? note 1. ~? .qa:.$~ if device wh.?~~ls,@dressed during this cycle uses vma, then the data bus will go to the high impedance three-state condition. dependi,n,~ 4q b~ capacitance, data from the previous cycle may be retained on the data bus. note 2. data is,@w~@ bv the mpu, note 3. whil@?~$~,~pu is waiting for the interrupt, bus available will go high indicating the following states of the control lines: vma is lo~@~ess bus, rm, and data bus are all in the high impedanca state. ,,: ?w:.? ?~.,~jl, ~.~> ,: , ,<. j*:\\> ?,$. ,.,.!;. ,. ..:,+ ....,y. .:?>? ~?~i>,, ,; ]*;i~.?j> .l,*!<. - th$w.~ory location specified by the contents of the index re@ter (recall that the label ?x? is reserved to designate the index register). since there are instructions for manipulating x during program execution (ldx, inx, dec, etc.), the in- dexed addressing mode provides a dynamic ?on the fly? way to modify program activity. the operand field can also contain a numetical value that will be automatically added to x during execution. this for- mat is illustrated in figure 33. when the mpu encounters the ldab (indexed) opcode in location 5006, it looks in the next memory location for the value to be added to x (5 in the example) and calculates the required address by adding 5 to the present index register value of 4~. in the operand format, the offset may be represented by a label or a numerical value in the range o-255 as in the example. in the earlier example, staa x, the operand is equivalent to o, x, that is, the o may be omitted when the desired address is equal to x. table 11 shows the cycle-by-cycle operation for the indexed mode of address- ing, @ motorola semiconductor products inc. 26 figure = ? immediate addressing mode figure 30 ? direct addressing mode mpu % ram program memory i pc instr data general flow mpu m acca m ram mpu m ram ador * data program memory ii program memory ?c=?oo?w ?c?* example mpu g acca m ram example 1 address mode cycle vma ?!i<,,l>; and 1 nstructions cycles # line addrass bus data bus .\.!),, , 1?,? .f???*,.., adc eor 1 1 op code address .es??$% ?? ~\ 1 op code add lda and ora 2 2 1 op code address+ 1 ?~+? i figure 31 ? extended addressing mode mpu mpu r % ram data program memory ram i --- . . ador pc addr = 300 program memory i w instr addr @ lda b 300 pc = 5006 5009 m addr ? aodr > 256 general flow example table 9 ? extended mode cycle-by-cycle address mode cycle vma and instructions cycles = line 6 9 sts stx 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 op code address of operand (high order byte) address of operand (low order byte) irrelevant data (note 1 ) operand data (high order byte) operand data (low order byte) op code jsr address of subroutine (high order byte) address of subroutine ( low order bvte) 3p code of next instruction l 1 0 0 1 1 1 1 return address (low order bvte) return address (high order bvte) irrelevant oata (note 1 ) irrelevant data (note 1 ) address of subroutine (low order bvte) op code jump address (high order bvte) jump address ( low order bvte) 3 op code address + 1 ii op code address + 2 1 op code address 1 op code address of operand (high order bvte) address of operand (low order bvte) operand data w op code address of operand (high order bvte) address of operand (low order bvte) operand data (high order bvte) operand data (low order bvte) op code address + 2 i 1 address of operand 1 address of operand + 1 1 op code address 1 op code destination address (high order bvte) destination address ( low order bvte) irrelevant oata (note 1 ) data from accumulator op code op code address + 1 1 op code address + 2 1 operand destination address 1 operand destination address o op code address 1 asl lsr asr neg clr rol op code address + 1 ii address of operand (high order bvte) address of operand (low order bvte) current operand data irrelevant data (note 1 ) new operand data (note 2) op code address + 2 i 1 address of operand 1 com ror dec tst inc 6 address of operand 1 address of operand o ~te 1. it device which is addressed during this cvcle uses vma, then the data bus will go to the high impedance three-state condition, depending on bus capacitance, data from the previous cycle mav ba retatned on the data bus. note 2. for tst, vma = o and operand data does not change, @ motorola semiconductor products inc. 28 figure 32 ? relative addressing mode mpu ram 1 proaram i megory pc instr. offset (pc + 2) next instr. pc pc t addr = inox + offset mpu a ~am s program memorv 5008 beq 15 5010 next instr. mpu . ..3 . . . -~ 1,? ..,. offset< 255 ,,. . . .,.y # ... ?k,\*a\. . table 10 ? relative mode cycle-by-cycle operation ..,$~~ ,>? .+.. address mod.@x,.,.j:, ? cycle vma rig and i nstruc,$~~ ?r???*?f cycles + line address bus line data bus 1 {t ?: .>,. $?{,, ,. i.> ~:+,, \*>: .+ bcc bh#~?b~b? 1 1 op code address 1 op code bcs ,@&~@>>@~ l 2 be q $~@\$~<. bra 4 1 op code address + 1 1 branch offset bg5 &&t ;;: 3 0 op code address t 2 1 irrelevant data (note 1 ) b&?$~?*rm i ?t., a:? ~- 4 0 branch address 1 irrelevant data (note 1 ) bs ~: 1 1 op code address 1 op code 2 1 op code address+ 1 1 branch offset 3 0 return address of main program 1 irrelevant data (note 1 ) 8 4 1 stack pointer o return address (low order byte) 5 1 stack pointer ? 1 0 return address (high order byte) 6 0 stack pointer ? 2 1 irrelevant data (note 1 ) 7 0 return address of main program 1 irrelevant data (note 1 ) 8 0 subroutine address 1 irrelevant data (note 1 ) . . ..-. . . . . -., . . . ,, .,. ,., . . . . . . .- ?j.. ,-? note 1. if device which is addressed during this cycle uses vma, tnen tne uata bus wiii go to tne nlgn !mpeaance ~nree-state conut~!un. depending on bus capacitance, data from the previous cycle may be retained on the oata bus. @ motorola semiconductor products inc. 29 ? i table 11 ? indexeo mooe cycle-by-cycle address mode cycle vma r 1~ and instructions cycles # line address bus line deta bus i indexed ? jmp adc eor add lda and ora bit sbc cmp sub cpx lds ldx sta asl lsr asr neg clr rol com ror dec tst inc ;ts 3tx 4 5 6 6 ? t 2 3 4 t 2 3 4 5 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 7 t 2 3$$ ?q; ;@p 6 7 t 2 3 4 5 6 7 8 ? 1 1 0 0 t 1 0 0 1 op code address op code address + 1 index register index register plus offset (w/o carry) op code address op code address + 1 index register index register pi us offset (w/o carry) index register plus offset op code address op code address+ 1 index register index register plus offset (w/o carry) index register plus offset index register plus offset + 1 op code address op code address + 1 ,,,, .7>.,, ,,+ y:>, index register b:# ,$ package dimensions case 711-w (plastic) motorola reserves the right to make changes to any products herein to improve reliability, function or design. motorola does not assume any iiabilityarising out of the application or usa of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. @ motorola semiconductor products inc. 31 i @ m070rola semiconductor products inc. 3501 ed bluestein blvd austin, texas 78721 l a subsidiary of motorola lnc ? ? *,1,,,-, pr,m,, ,. ?,. ,-84 1.,,,,0 li,,m .20206 1s,000 ,,,,7,12 ?-. ? ??.??? ?. ?-. ?. ???- . . . . . . |
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